The method of implementing a particular function using multiple processing paths is conventionally referred to as parallel processing. When an input signal is treated as multiple signals that are segmented in time (e.g., a series of subsequences that collectively represent a single, complete sequence), the parallel processing operation typically is said to employ techniques of time-interleaving, polyphase decomposition, or multirate processing. When an input signal is treated instead as multiple signals that are segmented in frequency (e.g., a series of narrow frequency bands that represent a single, wider frequency band), the parallel processing operation typically is said to employ techniques of frequency interleaving, or frequency decomposition. To improve instantaneous bandwidth, multiple data converters can be operated in parallel using these time interleaving (time slicing) and/or frequency interleaving (frequency slicing) techniques. In conventional time interleaving, a high-speed sampling clock is decomposed into lower-speed sampling clocks at different phases. Each converter in the time-interleaved array is clocked with a different clock phase, such that the conversion operation is distributed in time across multiple converters. While converter #1 is processing the first sample, converter #2 is processing the next sample, and so on. In conventional frequency interleaving, the total bandwidth of an input signal is divided into multiple, smaller sub-bands. Each sub-band is individually downsampled and converted at a subsampled rate, before, e.g., being upsampled and recombined at a full rate. While converter #1 is processing the first sub-band, converter #2 is processing the second sub-band, band, so on. For both time-interleaved and frequency-interleaved operations, a final output signal is constructed (i.e., reconstructed) by combining the outputs of the parallel converters.
According to one representative implementation of a time-interleaved converter (e.g., ADC 10), shown in FIG. 1A, a full-rate input signal (e.g., signal 2 sampled at fS) is converted to a total of m sub-rate signals (e.g., signals 12A-C sampled at
            1      m        ·          f      S        )within serial-to-parallel demultiplexer 11. According to conventional multirate processing, the output of each parallel processing path (e.g., outputs 12A-C) is the sequence of samples that would be produced by subsampling, at a particular sample-time offset (i.e., at a particular subsampling phase), the sequence of samples representing the input signal (i.e., the input signal is a complete signal and the output of each parallel path represents a different polyphase component of that complete signal). A compete analog version of the input signal is constructed at the output of the converter (e.g., complete analog signal 4) through a process which involves: 1) delaying each of the subsampled sequences (subsequences) in incrementally larger multiples of the full-rate period 1/fS (e.g., time-offset resampling by registers 13A-C); 2) converting each of the delayed subsequences from discrete-time samples to continuous-time signals (e.g., digital-to analog conversion by DACs 14A-C); and 3) summing together each of the delayed, continuous-time signals (e.g., summation by combiners 18A&B). Each parallel path of converter 10 (e.g., delay paths 16A-C) operates at a submultiple of the overall sampling rate, due to the reduced amount of data contained within each of the subsampled sequences. The ratio of the overall sampling rate (i.e., the full-rate of the input signal) to the parallel subsampling rate (i.e., the sub-rate associated with each parallel processing path) conventionally is referred to as the polyphase decomposition factor, and is generally equal to the number of parallel processing paths.
According to one representative implementation of a frequency-interleaved converter (e.g., ADC 20), shown in FIG. 1B, parallel signal processor 21 converts a full-bandwidth (BF) input signal (e.g., signal 2 sampled at fS=2·BF) into a total of m baseband signals with a minimally overlapping fractional bandwidth (e.g., signals 12A-C with bandwidth
      1    m    ·      B    F  and subsampled rate
                    1        m            ·              f        S              )    .More specifically, the input signal spectrum is divided into narrowband segments to produce fractional bandwidth signals, which are separated out and downsampled (downconverted) to produce sub-rate outputs 22A-C. A compete analog version of the input signal is constructed at the output of the converter (e.g., complete analog signal 4) through a process which involves: 1) converting each of the resulting baseband signals (e.g., sub-rate signals 22A-C) from the digital domain to the analog domain (e.g., digital-to analog conversion by DACs 23A-C); 2) upconverting each of the analog signals from baseband to a central frequency that coincides with the fractional bandwidth originally occupied by the signal (e.g., upconversion by mixers 24A-C to the signal's previous frequency band); and 3) summing together each of the upconverted, continuous-time signals (e.g., summation by combiners 28A&B). Each parallel path of converter 20 (e.g., frequency paths 27A-C) operates at a submultiple of the overall sampling rate, due to the reduced signal bandwidth in each of the subdivided, downconverted bands.
Another parallel processing structure that is associated with conventional data conversion (e.g., ADC and DAC), is multi-stage delta sigma (ΔΣ) modulator 30, illustrated in FIG. 1C. A conventional multi-stage ΔΣ modulator, or MASH modulator, uses multiple processing stages to shape away from a frequency band of interest, the conversion noise introduced by a coarse quantizer. A modulator with a second-order response, shapes the quantization noise of a coarse quantizer with a transfer function HNTF(z) given byHNTF(z)=1+α·z−1+z−2,where z is the Z-transform variable representing a delay of one sample period, and the coefficient α determines the location of a spectral null in the noise-shaped response. Multi-stage (i.e., MASH) structures provide a means for increasing the overall order of a noise-shaped response, without increasing the order of the noise shaping performed by an individual stage. In a conventional multi-stage arrangement, a first stage processes an input signal, and subsequent stages process the residual noise of the previous stage (e.g., first stage 36A processes input signal 32A, and second stage 36B processes residual noise 32B from the output of adder 31C). Consequently, if each of stages 36A&B of modulator 30 performs noise shaping with a second-order response, then it can be shown that the overall modulator provides the benefit of fourth-order shaping with transfer function HNTF2(z), given byHNTF2(z)=(1+α·z−1+z−2)2,such that more conversion noise (e.g., from coarse quantizers 34A&B) is shaped away from a frequency band of interest. To realize this benefit, however, additional processing is needed for signal reconstruction and combining (e.g., filter and summation within circuit 36C). For second-order stages, this additional processing involves: 1) applying a transfer function of HNTF(z) to output 35B of the second stage, using two delay operations (e.g., within pipeline registers 37A&B of stage 36B), one multiplication operation (e.g., within multiplier 39 of combiner 36C), and two addition operation (e.g., within adders 38A-B of combiner 36C); and then 2) combining filtered output 35C of the second stage, with output 35A of the first stage, to produce final output 35D.
To keep pace with advances in the digital information processing bandwidth of computers and signal processors, time/frequency interleaving and multi-stage noise shaping techniques are becoming increasingly utilized as a means of enhancing the capabilities of conventional D/A converters. To operate at the highest possible sampling rates, therefore, circuits capable of wideband signal reconstruction (e.g., continuous-time summation) are needed for conventional time-interleaved D/A converters, such as converter 10 of FIG. 1A, for conventional frequency-interleaved converters, such as converter 20 of FIG. 1B, and for conventional multi-stage modulators, such as modulator 30 of FIG. 1C. Circuits used for the summation of continuous-time signals conventionally are referred to as power combiners (or splitters, since the same circuit is often able to split a signal into two separate paths). Resistive network 40A, illustrated in FIG. 2A, represents one type of conventional power combiner. Purely resistive networks, such as two-way combiner 40A, offer wideband operation at the expense of what generally is an unacceptably high level of signal attenuation (e.g., 6 dB of attenuation for a 2-way combiner). A second type of conventional power combiner, which overcomes the problem of unacceptably high signal attenuation, is transformer 40B of FIG. 2B. Although as a signal combiner, the transformer combines signals with less attenuation, transformers generally are not well suited for high frequency operation due to the poor high-frequency coupling properties of conventional ferrite core materials.
A third type of conventional power combiner is represented by circuits which perform continuous-time signal summation and are constructed from actual or “artificial” transmission lines. The term “artificial” transmission line is conventionally used to describe ladder networks, such as passive ladder networks 45A&B of FIGS. 3A&B, respectively, which consist of concatenated inductor-capacitor sections (e.g., L-section 49), because such a structure approximates the general properties of an actual transmission line (e.g., characteristic impedance, propagation delay, minimal attenuation, etc.). Each of passive ladder networks 45A&B comprises L-sections (e.g., L-section 49) with a series inductance L (e.g., from discrete inductor 43) and a shunt capacitance C (e.g., from discrete capacitor 44) that are joined together at a junction point (e.g., interior junction point 46). At the terminal junctions points (e.g., outer junction points 47A&B), which are located on each end of the ladder network, a resistive element provides a shunt termination that is equal to the characteristic impedance of each L-section, given by Rterm=√{square root over (L/C)} (e.g., the shunt termination provided by resistors 42A&B). Ladder network 45A employs a configuration where the first and last reactive elements are series inductors with inductance equal to ½·L, and ladder network 45B employs a configuration where the first and last reactive elements are shunt capacitors with capacitance equal to ½·C. Each L-section of ladder networks 45A&B, introduces a propagation delay tPD oftPD=√{square root over (LC)}, and overall, each circuit produces a lowpass response with a bandwidth that is approximately given by
  BW  ≈            1              π        ⁢                  LC                      .  The upper cutoff frequency of the lowpass response preferably is greater than the maximum frequency at which the apparatus is intended to operate.
Examples of conventional circuits which employ passive ladder networks for continuous-time summation are the Wilkinson power combiner (e.g., power combiner 50A illustrated in FIG. 4A) and the branch-line coupler (e.g., coupler 50B of FIG. 4B). Combiner 50A combines two input signals into one output signal, utilizing two unterminated ladder networks (e.g., first ladder network 57A and second ladder network 57B) in a configuration where: 1) the input of first ladder network 57A is coupled to the input of second ladder network 57B by a resistor with value √{square root over (2)}·Rterm ohms, where Rterm is the characteristic impedance of each ladder network (e.g., input 55A is resistively coupled to input 55B at terminal junction points 51A&B); and 2) the output of first ladder network 57A is coupled to the output of second ladder network 57B by a short circuit (i.e., the output of the first ladder network is directly coupled to the output of the second ladder network at terminal junction points 53A&B). Such a configuration is advantageous in that for signal sources and signal loads having a matched impedances equal to Rterm/√{square root over (2)}, there is: 1) minimal attenuation (loss) of narrowband input signals propagating from the input ports to the output port; and 2) maximum isolation (loss) between narrowband input signals propagating from one input port to the other input port (i.e., minimal attenuation and maximum isolation occurs when the impedance seen looking back into the source on each of input ports 55A&B is equal to Rterm/√{square root over (2)}, and the impedance seen looking into the load on output port 56A also is equal to Rterm/√{square root over (2)}). Such a configuration is disadvantages for high-speed (wideband) data converter applications, however, because the low-frequency components and/or high-frequency components of wideband input signals are significantly attenuated by the apparatus. Another disadvantage is that the current sources and loads typically utilized in data converter applications, have uncontrolled impedances (e.g., source and load impedances typically are not controlled to equal Rterm/√{square root over (2)}).
Combiner 50B, illustrated in FIG. 4B, is a representative example of a conventional branch-line coupler. Combiner 50B is similar to combiner 50A in that it utilizes two passive ladder networks (e.g., ladder networks 57C&D) to combine two input signals into one output signal. Each end of first ladder network 57C is unterminated and is coupled to an input signal (e.g., input signals 55C&D). One end of second ladder network 57D is terminated in a characteristic impedance of Rterm (e.g., terminated by shunt resistor 59), and the other end is unterminated and coupled to an output signal (e.g., output signal 56B). In combiner 50B, the ends of first ladder network 57C are coupled to the corresponding ends of second ladder network 57D by inductors, such that: 1) input 55C is inductively coupled (e.g., via inductor 58A) to the terminated end of network 57D at terminal junction points 52A&B; and 2) input 55D is inductively coupled (e.g., via inductor 58B) to output 56B at terminal junction points 54A&B. With respect to high-speed data converter applications, combiner 50B has advantages and disadvantages which are similar to those of combiner 50A, but combiner 50B has the additional disadvantage that input signals 55C&D are combined in quadrature to form output signal 56B, such that during the combining process, one of the input signals gets phase shifted by 90 degrees relative to the other input signal.
In addition to the representative power combiners described above, active elements are sometimes incorporated into ladder networks (i.e., forming active ladder networks) as a means of improving the bandwidth and signal attenuation associated with certain types of conventional power combiners (and power splitters). For example, conventional power combiner 60 illustrated in FIG. 5A, sometimes is referred to as a distributed power combiner. Combiner 60 produces a single output (e.g., output 63A) by summing two different input signals (e.g., inputs 64A&B), using: 1) two input transmission lines (e.g., active ladder networks 65B&C); 2) a single output transmission line (e.g., active ladder network 65A); and 3) multiple active elements (e.g., gain cells 62A&B). In a conventional distributed combiner, such as circuit 60 of FIG. 5A, the intrinsic capacitances of active elements (e.g., the intrinsic input or output capacitance of gain cells 62A&B) are grouped with discrete inductors (e.g., inductor 61) to form the reactive impedance segments (e.g., L-sections 67A&B) of an artificial transmission line (e.g., input transmission lines 55B&C and output transmission line 65A). Grouping multiple active elements with discrete inductors to form L-sections, results in an overall bandwidth BW that is approximately determined by the bandwidth of each L-section according to
      BW    ≈          1              π        ⁢                              LC            gm                                ,where L is the total inductance associated with each L-section, and Cgm is the shunt (e.g., intrinsic input or output) capacitance associated with an active device in each L-section. Furthermore, the overall (voltage) gain AV of combiner 60 increases linearly as the number of active elements increases, according to
            A      V        =                  1        2            ·      n      ·              g        m            ·              R        term              ,where: 1) n is the equal number of active elements (i.e., gain cells) included in an input transmission line; 2) gm is the transconductance associated with each gain cell; and 3) Rterm=√{square root over (L/Cgm)} is the terminating resistance for an artificial transmission line (i.e., the shunt resistance at a terminal junction point). For any input signal, therefore, the gain of combiner 60 is independent of bandwidth, and depends only on the number of gain cells distributed across a ladder network (i.e., the number of active device in each input transmission line). The gain cells associated with each of the reactive impedance segments typically are implemented using conventional topologies that include: 1) the common-source amplifier 80A of FIG. 6A; 2) the variable-gain cascode 80B of FIG. 6B; 3) the broadband cascode 80C of FIG. 6C; and/or 4) the variable-gain/delay amplifier 80D of FIG. 6D.
Conventionally, a distributed power combiner comprises multiple input transmission lines and a single output transmission line, where: 1) one end of each transmission line is terminated (e.g., by shunt resistors 69A-C) in the characteristic impedance of each reactive impedance segment (i.e., L-section), given by Rterm=√{square root over (L/Cgm)}; 2) the other (opposite) end of each transmission line is unterminated and used for accepting input signals or providing output signals; 3) the number of input transmission lines establishes the number of input signals that are combined into a single output signal (i.e., the power combination ratio); 4) the relative number of active devices (i.e., gain cells) associated with each input transmission line, determines the proportion with which the input signals are combined into a single output signal; and 5) the total number of transmission lines (i.e., the number of input transmissions lines plus the number of output transmission lines) is equal to one more than the number of input signals. Similar structures, such as circuit 70 shown in FIG. 5B, can be utilized to split (divide) an input signal (e.g., input signal 74A) into multiple output signals (e.g., output signals 73A&B). Conventionally, a distributed power divider (e.g., circuit 70) comprises multiple output transmission lines (e.g., active ladder networks 75A&B) and a single input transmission line (e.g., active ladder network 75C), where: 1) one end of each transmission line is terminated (e.g., by shunt resistors R69A-C) in the characteristic impedance of each L-section, given by Rterm=√{square root over (L/Cgm)}; 2) the other (opposite) end of each transmission line is unterminated and used for accepting input signals or providing output signals; 3) the number of output transmission lines establishes the number of output signals that are separated out (split) from a single input signal (i.e., the power division ratio); 4) the relative number of active devices (i.e., gain cells) associated with each output transmission line determines the proportion with which the output signals are split from a single input signal; and 5) the total number of transmission lines (i.e., the number of input transmissions lines plus the number of output transmission lines) is equal to one more than the number of output signals.
Although distributed combiner 60 potentially can provide sufficient wideband operation for use in high-speed data converter applications, such a combiner suffers from at least two significant problems. One significant problem is that a conventional distributed combiner (e.g., combiner 60) is designed for use with matched impedance sources and loads, and the current sources and loads typically utilized in data converter applications have uncontrolled impedances (e.g., source and load impedances typically are not controlled to equal Rterm). A second significant problem is that during the combining process of a conventional distributed combiner, one of the input signals gets appreciably phase shifted relative to any other input signal. In a conventional distributed combiner, the input signals are combined out-of-phase (i.e., combined with unequal phase shifts) because one input signal is subjected to the propagation delay of a larger number of L-sections than the other input signal (e.g., input signal 64A propagates to output 63A through a total of four L-sections, while input signal 64B propagates to output 63A though a total of only three L-sections). Conventionally, the amount of phase shift applied to any input signal is not considered a critical design parameter and is unconstrained. The present inventor has discovered that in high-speed data converter applications, the sampling skew resulting from out-of-phase signal combining introduces nonlinear distortion that degrades conversion precision.
Distributed networks have been utilized to extend the operating bandwidth of conventional apparatuses that perform the functions of signal amplification, power dividing, and power combining. Conventional use of distributed networks, however, has not resulted in a means of signal reconstruction (i.e., continuous-time summation) that exhibits the properties needed for time-interleaved, frequency-interleaved, or other parallel structures for D/A conversion. In high-speed D/A applications, conventional signal combiners suffer from one or more deficiencies related to signal attenuation, uncontrolled impedances, or out-of-phase combining. To support advances in analog and digital signal processing speeds, therefore, the need exists for a distributed signal reconstruction apparatus that offers a level of performance that is not possible through conventional means.